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- _VHDL CODE
- __AND Gate
- __OR Gate
- __NOT Gate
- __NAND Gate
- __NOR Gate
- __XNOR Gate
- __XOR Gate
- __Half Adder
- __Half Substractor
- __Full Adder
- __4Bit UP COUNTER
- __4Bit DOWN COUNTER
- __D Flip_Flop
- __SR Flip_Flop
- __JK Flip_Flop
- __T Flip_Flop
- _UNIT1
- __Syllabus
- __Introduction To VHDL
- __Language Elements
- __Operators
- _UNIT2
- __Clock Skew
- __Jitter
- __Clock Distribution
- __Power Distribution
- __Power Optimization
- __Interconnecting Routing
- _UNIT3
- AI
- _UNIT 1.FOUNDATION
- __Introduction To AI
- _UNIT 2:Searching
- _UNIT 3:Knowledge Representation
- IOT
- _UNIT 1:Fundamentals of IOT
- _UNIT 2:Sensors Networks
- _UNIT 3:Wireless Technologies for IOT
- _UNIT 4:IP Based protocols for IOT
- _UNIT 5:Data Handling & Analytics
- _UNIT 6:Applications of IOT
- CN&S
- _UNIT 1:Introduction to LAN(Local Area Network)
- _UNIT 2:Network Layer Part 1
- _UNIT 3:Network Layer Part 2
Showing posts with the label VHDL CODEShow all
VLSI D&T
T Flip_Flop
T Flip-Flop CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity TFF is port(t, clk, rst :in STD_LOGIC; qb:out STD_LOGIC);…
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VLSI D&T
JK Flip_Flop
JK Flip-Flop CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity JKFF is port(j, k, clk, rst :in STD_LOGIC; q, qb:out STD_LO…
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VLSI D&T
SR Flip_Flop
SR Flip-Flop CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity SRFF is port(s, r, clk, rst :in STD_LOGIC; q, qb:out STD_LOG…
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VLSI D&T
D Flip_Flop
D Flip-Flop CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity DFF is port(D, clk, rst :in STD_LOGIC; y:out STD_LOGIC); e…
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VLSI D&T
4Bit DOWN COUNTER
4 BIT DOWN COUNTER CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity 4bit_counter is port(clk, rst, mode:in STD_LOGIC; …
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VLSI D&T
4Bit UP COUNTER
4 BIT UP COUNTER CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity 4bit_counter is port(clk, rst, mode:in STD_LOGIC; …
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VLSI D&T
Full Adder
Full Adder CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity full_add_df is port(a,b,cin:in STD_LOGIC; sum, carry:out STD_L…
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VLSI D&T
Half Subtractor
Half Subtractor CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity half_sub_df is port(a,b:in STD_LOGIC; diff, borrow:out…
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VLSI D&T
Half Adder
Half Adder CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity half_add_df is port(a,b:in STD_LOGIC; sum, carry:out STD_LOGIC…
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XOR Gate
XNOR Gate
VLSI D&T
VLSI D&T
VLSI D&T
VLSI D&T
LATEST POSTS
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Power Distribution QUE::Explain power distribution and power optimization technique . Power Distribution presents several significant probl... -
FEATURES OF 8051 MICRO-CONTROLLER 8 bit DATA Bus. 8 bit Arithmetic and Logical Unit. 128 bytes of on chip data memory. 4K of on chip program... -
SIMPLE ASSEMBLY LANGUAGE PROGRAM Add two 8 bit number 35H and 42H. Store the result on memory location 50H. Program- ORG 0000H MOV A,#35H;..... -
Interconnecting Routing QUE::Explain interconnecting routing technique. The basic objective of this design are area , delay, and power fl... -
Power Optimization QUE::Explain power optimization technique. QUE::Explain power distribution ad power optimization technique. Power opt... -
ADVANTAGES AND DISADVANTAGES OF 8051 MICRO-CONTROLLER ADVANTAGES The hardware is less because of single chip microcomputer system. This redu... -
Binary Adders are the Combinational logic circuits used to perform the addition of the two binary digits.An adder is performs addition of nu... -
4 BIT UP COUNTER CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity 4bit_counter is port(clk, rst, mode:in STD_LOGIC; ... -
NOR Gate CODE library IEEE; use IEEE STD_LOGIC_1164.all; entity nor_df is port(a,b:in STD_LOGIC; y:out STD_LOG... -
It is an electronic circuit having one or more than one input and only one output is based on certain logic.LOGICAL GATE are AND gate, OR ga...
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